RAM type/speed for new system

[Guest D17S]

No hurry. Take another shot when you have time. Dem vibes, dem vibes. I'm starting to feel those harmonies already. We'll get a bit more technical, eventually. Little steps.

[Guest Nick_N]

Its very late and I am heading to bed after a long day on the GEX EU projectI will explain more tomorrow if necessary however what you are showing me is a situation where you are better off on the higher bandwidth due to the limitations of CAS in 2x2GB and the fact that 1T is 'unknown' The sticks I am using are proven samsung chips for the 1T rating even though Corsair rates the sticks 2T.If you will recall I said that CALWI is not the holy grail although the zone is where you want to be by hardware design.... but when it is close but not possible to hit CL due to hardware limits there are other ways to compensate to a certain extent.You are using my primary CL timing to make your assessment on CALWI. What the charts and descriptions do not discuss are timings outside CL. The sticks I posted are not only running 1T, they are doing so lower than rated on the subs and as such timings such as tRFC are running t14 lower than JDEC and t28 lower than the Corsair XMP, etc. This will have defined effect on true CALWI and will place it lower than the standard chart suggests although still not in the 'red-hot zone' of 7.5 or less. In this situation and on the same subs with exception of tRAS, I can vary the result somewhat with good results. I can take a tRAS of 20 which is a bit outside the desired using the tRAS formula .... http://forums.avsim.net/user_files/189093.jpgOr I can optimize tRAS to 17 where it belongs, reduce FSB a hair for 100% stability and get this result... http://forums.avsim.net/user_files/189094.jpgFor real world I prefer the 2nd because tRAS is optimized and in both cases the sticks are @ 6 MCH which is quite low for 2x2gb and also an unknown value with the DDR3 1600 product.I would estimate those sticks are running in the 8.2-8.4 range max given the subs and other factors involved however when you add in I am able to manually set tRD lower, that means the true CALWI value drops again placing it just under 8, easy. In this case it is not giving me tRD6 on its own due to CL but it does allow me to force it meaning the CALWI cart value drops, just not as much as if I was running CL7Throw in a 8 multiplier on a B3 processor at above 3.6GHz stable and that is one solid clock even if CAS is not perfect.The DDR3 2200 sticks in the x48 tower are running CAS7 at DDR3 2000 placing them at a CALWI of 7 or red hot especially @ 1T. It will be at least another month before those will hit the market from what I am told.

[Guest Nick_N]

here are a few P5E3 Premium snagshttp://forums.avsim.net/user_files/189104.jpghttp://forums.avsim.net/user_files/189105.jpgThe board is young and they are working as usual on BIOS updates however of all the boards I played with I found it one of the most stable for clocking. I do not know all the limits of it in terms of hardware.. you should probably check and verify CPU/memory compatibility with BIOS revision

[Guest D17S]

Was there any syncing going on there? If so, how so?

[Guest Nick_N]

SamI find that type of communication unbecoming of someone who is intellegent and who posseses a high technical aptitudeAlthough not quite technically correct in it use for midnight after a long day, the term was used on the same lines Intel uses to describe the IP-based prefetcher and their approach to memory disambiguation which I am sure you are aware happens to be one of the reasons for the C2 advantage over the AMD method"Working in concert with memory disambiguation"http://www.intel.com/technology/magazine/c...ss-0906.htmsons "the IP-based prefetcher reduces memory latency and improves performance."Anything that can be done to place the memory buss in a lower latency state and get data to and from the processor by removing the bottleneck placed on the buss by the northbridge is getting the speed of the data in sync with the processor ability and assists the IP-based prefetcher in its job. 'sync' meaning "Working in concert"I hope that helps

[Guest D17S]

The smartest thing about me is that I know I'm dumb as a rock. "Why is the sky blue" is hardly a small minded question. It only expresses a curiosity about a phenomenon that is generally (even locally) unknown and that might have not fully considered. Let's consider it now. Small steps. Little words. " -- Anything -- (that can be done to place the memory buss in a lower latency state and get data to and from the processor by removing the bottleneck placed on the buss by the northbridge) -- is getting the speed of the data in sync -- (with the processor ability and assists the IP-based prefetcher in its job.)"OK, what's "sync?" (I'm supposing that "Anything" might be somewhat of a generalization).

[Ted Striker 338]

In "sync" to me means two components running at the same speed and in phase so the little electron batons can be passed efficiently. All the busses running 1:1. But from what I've read from you before Nick is that you're better off overclocking the memory buss with respect to CPU buss. How this is in sync is beyond me, but I'm not nearly as smart as Sam. I'll be the first to admit, I'm as "dumb as dust" when it comes to this stuff, but it is interesting reading the discussions. Sometimes I feel like I'm back in college trying to find a teaching assistant to explain in layman's terms what the Phd research professor just said. :-eek I read your link (by the way if you change the .htmsons to .pdf the link works), but didn't get much useful information from it. It read like what may have started out as a good tech article got neutered by the marketing and legal departments. Maybe it was to far over my head.What I would like to know is, do know any any good idiots guides to building and optimizing a computer system that explains all this at an undergraduate level? Specifically identifying and resolving data flow bottlenecks?Now I feel like Oliver Twist asking for more porridge... :-hahGet some rest first though,Ted

[Noel 4,563]

>The DDR3 2200 sticks in the x48 tower are running CAS7 at DDR3>2000 placing them at a CALWI of 7 or red hot especially @ 1T.>It will be at least another month before those will hit the>market from what I am told.Those are not 2gb sticks are they? I won't work with 2GB only of memory, plus if the suckers won't do 4x1GB then I'll have to settle for something more conservative.Nick, what is the BEST 2gb x 2 kit available today in DDR3? I have a possible op to swap the DOA P5E for credit on a P5E3-Premium. I am maybe interested in very good memory solution but not the top. What can you recommend? I'd also like to keep memory and board overclocking in the safe zone, or at least safer!QX9650 w/ Retail HSF|8GB Muskin PC-6400|ASUS P5E|EVGA 8800GT @700|Seagate SATA 2 x 4|Seagate Cheetah 15K.x|XP Pro|Vista 64--soon to be installed

[Noel 4,563]

>>>Sam>>I find that type of communication unbecoming of someone who is>intellegent and who posseses a high technical aptitude>>>>Although not quite technically correct in it use for midnight>after a long day, the term was used on the same lines Intel>uses to describe the IP-based prefetcher and their approach to>memory disambiguation which I am sure you are aware happens to>be one of the reasons for the C2 advantage over the AMD>method>>"Working in concert with memory disambiguation">>http://www.intel.com/technology/magazine/c...ss-0906.htmsons>>>"the IP-based prefetcher reduces memory latency and improves>performance.">>Anything that can be done to place the memory buss in a lower>latency state and get data to and from the processor by>removing the bottleneck placed on the buss by the northbridge>is getting the speed of the data in sync with the processor>ability and assists the IP-based prefetcher in its job. >>'sync' meaning "Working in concert">>>I hope that helpsHere here! Well said!I have had an appreciation for syncing all along. My pet peave has been in getting some sort of sense as to how much it matters when it gets down to user experience. When I had my old machine running at 1050Mhz/51.8ns/CALWI 7, I did experience best ever performance. I'm certain. And I'll stand by 98% of perfection over 90% is arguably worth something. $1000? That's that hard part! I guess one thing that has driven this for me is that THIS TIME, I decided to purchase very high end parts. Well, I did with my QX. It's a great processor. Cool, and just loves to waltz. I think she needs a better memory subsystem to dance with tho!Nick, Sam, anyone! Give me a DDR3 2x2Gb kit that will get me very close to max (assuming Nick's 1T x48 is pretty much max).Noel

[Guest D17S]

Yea, I got it too. Techno-jabber city."Sometimes I feel like I'm back in college trying to find a teaching assistant to explain in layman's terms what the Phd research professor just said." . . . Me too, except I'm there all the time!There are some things I know very well. When I explain these things to others, I have to be very careful to simplify entirely. My ability to communicate is often sabotaged by the inevitable submersion of complicated concepts into a heart felt sense of common sense. This sense of "obvious" is all in my mind, but not in others. There is one other thing I've learned. If I do not fully understand the topic, simplification becomes impossible. However, if I Do have a clear grasp, simplification becomes a breeze: a joy really, because I can teach it. The most complicated thing I know I can explain to a 10 year old.I always become a bit concerned when the professor can't clean it up. I see this constantly even (especially) in college classrooms. In these cases, I become the "Student from Hel-." The profs are used to a class full of (less assertive) 19 year olds.It's clear that simply putting the peddle to the metal with by running whatever numbers we can see to their highest possible level is not the trick. Faster is not necessarily better . . . and back to an original observation, slower is not necessarily worse. OK, so let's try some more: 1) What things are working in concert?2) What is (are) their electrical properties? (BTW: Yes, I know there are no little gears in there . . . but I wish there were!) 3) Which of these electrical properties are important for "syncing." 4) How can these properties be "synced."

[Noel 4,563]

Good questions Sam, and I agree Nick has not really addressed them very well. From the link Nick provided:"Working in concert with memory disambiguation, the IP-based prefetcher gathers memory contents before they are requested so they can be placed in cache and readily accessed when needed. By increasing the number of loads that occur from cache instead of main memory, the IP-based prefetcher reduces memory latency and improves performance."This suggests to me it is theoretically possible to engineer a processor subsystem that is so robust it can completely overcome latency issues inherent in the memory subsystem? Not saying this is what Core2 does, but apparently this is a key to how it holds up well against AMD's built in controller solution. If this is accurate, then definitely this discussion is still up in the air, and becomes this: what do you get for maxing out memory to get latencies of 42ns for example, and to what degree does memory/bus timing/bandwidth come into play when there are engineering features designed to offset latency and even bandwidth? Perhaps syncing is better viewed as "matching" components better in terms of their relative performance--relative to each other, so that there is not such a discrepancy between components in terms of bottlenecking. Even so Sam, I did see more consistent, mo betta results with the faster latency and bandwidth I was enjoying . . . or so it appeared.Sam, you are an artful writer, and I can totally imagine, and excellent teacher. Where are you going to school?QX9650 w/ Retail HSF|8GB Muskin PC-6400|ASUS P5E|EVGA 8800GT @700|Seagate SATA 2 x 4|Seagate Cheetah 15K.x|XP Pro|Vista 64--soon to be installed

[Guest D17S]

It's gonna be something like that. There Are gear teeth in there. Electricity's parallel to a machine's gear teeth is its "Frequency," or even more technically observed as Electrical Current Flow Direction Reversals (aka Alternating Current). It's simply astounding to recognize electrical current can change direction billions of times per second, but this is old hat. 4G is really nothing in the radio world. Phased array radar has been doing this for years. We're talking to Mars right now 'bout in that - "Bandwidth" - (aka "Frequency Range". We're talking to Mars at a radio frequency of about 4Ghz. It's in that "range," or it's in that "Frequency Range." Somewhere 'bout 4G. Bandwidth and Frequency Range are interchangeable terms) That brings up an interesting question. Why do they always talk about digital data speeds in terms of the Alternating Current (AC) property "Bandwidth?" There are 4 electrical events that occur during one of these AC cycles. 1) Current increases flow in a one direction, then 2) Current decreases flow in that direction. then3) Current increases flow in the other direction,then4) Current decreases flow in the other direction.(And BTW, There are no wavy things flying around. Waves are just the lines an engineer draws on a piece charting paper to represent this electrical dynamic. They tell us that radio is transmitted by "waves," but now we know better. These graph paper wave-looking-lines only represent increases and decreases in electrical flow.)On to computers: Ever heard the term "Quad Pumped"? These 4 AC events can either occur or not occur based on a switching scheme. Therefore, each AC cycle has the ability to communicate 4 "bits" of data. Each of these 4 events can either be switched on or off. Volia, Digital Data. This was the initial basis of the "Digital Revolution." Each Full AC cycle can (therefore) be considered by Intel Marketing, testosterone inspired name "Quad Pumped." That's why the bios uses (for instance) 400Mhz. That's the actual AC frequency and it's there for the more technical. Intel calls it 1600 for the under-informed masses. But what the heck Should it be called? It's not MHz, for sure. (Mr. Hertz is doin' underground flips!) I'm not sure really what that should be called. Let's make something up (in a minute).However (to continue this - Question - ) Data Has no choice but to "Catch a ride" at the MHz rhythm of this FSB highway. The CPU and memory might be considered bi-directional interchanges on either end of this highway. They HAVE to coordinate to the FSB's specifically defined "rhythm." In a default setup, the FSB frequency drives the CPU at a YX ratio and the ram at DDR (Double the FSB's Data Rate) But wait! Even this term "DDR" misleads. The FSB's "data rate" is really Quad Pumped to 4X its AC frequency (remember?). If ram was driven at 2 times the FSB's "data rate," it would explode. For instance, a 400MHz FSB "data rate" is a quad pumped 400MHz or 1600. We're gonna run ram at Double the FSB's Data Rate (DDR) or 1600 X 2? I don't think so! "DDR" is Such a stupid term. But at least we might be able to get a better one for that "Quad Pumped" number. Shall we call it the "FSB Data Rate" (FDR)? Sure, why not? The hippies got the last one. This one's ours. Hangin' in there? Of course you are. We had to make up a new application for the term "Data Rate," but that's OK. We're blazing a trail here. The FSB Really drives the memory at DACF - Double its AC Frequency, right? Yes, we had to make that up too. The terms we are presented by the industry are sooo bad. Ya gotta remember this was all invented in the 60s and they were all stoned.Sync actually makes a lot more sense than to be subjugated to a generic, catch-all term. There's definitely some syncing going on here. BUT HOW, Professor?

[Guest Nick_N]

>This suggests to me it is theoretically possible to engineer a processor subsystem >that is so robust it can completely overcome latency issues>inherent in the memory subsystem?Currently, no.. at least not right now by todays engineering standards and design and the main hurdle in that is physical size and stability along with the current architecture however theoretically, yes and do not be surprised if you start to see dedicated 'on board' memory which comes with motherboards in the next few years that may eventually have no limit to the processor, or... in perfect sync with it. Think of the current system as a memory defragmenter and a buffer cache similar to HDD technology (of sorts)... same as a hard drive defragment software can place files in name or other specified order on a drive for optimized recall and the drive technology can also have them in a electronic buffer ready for call ... the system on the microarchitecture side of the northbridge in the processor logs cache and physical memory addresses as data is called/processed and then prefetches from those addresses based on a algorithm developed by Intel. In other words... it learns and then "guesses" what will be called next. If the physical memory and buss is assisting in reducing the latency of the northbridge, then those prefetch blocks of data are moving to the processor that much faster and ready within the processor, that much faster.The thing you must realise is currently even with that prefetch, the processor is still waiting so what you are doing is assisting that system by working in concert with it.The fact that Intel is moving to the "tock" platform at the end of the year should be all the 'proof' you need. What does that platform do? It removes a great portion of the bottleneck between the memory and the processor by removing the current FSB influence and physical data buss limits on the memory controller, therefore the Nellie platform is doing what you are doing.. reducing the same bottleneck but Nellie does it with a exponential result. If you want to play... you gotta pay and boo-hoo if it cost 500-1000 more to play. I did not think I needed to explain and considered what was posted quite clear or if one did not understand terms they could look them up. I see from some posts perhaps I should have simplified the information. Sam your talents are going to waste here. I suggest you may wish to contact the current administration and offer services for speech writing, especially on issues like global warming.

[Guest Nick_N]

>Sync actually makes a lot more sense than to be subjugated >to a generic, catch-all term. There's definitely some syncing >going on here. >BUT HOW, Professor? http://www.youtube.com/watch?v=7mNDHTfdn1A

[Guest Nick_N]

>"Working in concert AKA Acting In ConcertTypically used to describe two or more investors working together to achieve the same investment goaland synonyms or short words used in place of the term could be several however 'sync' in that context is one of themOne of the main arguments I read here some time ago, Sam, and got a chuckle out of it is that because AMD bandwidth is significantly higher than Intel proves the use of it and latency has nothing to do with better performance. Well, in context that is partially true because its not being used efficiently by the current AMD CPU architecture. Intel makes much better use of it with the introduction of the C2. We only touched on one part of that change in this discussion which is the IP-prefetch system... AMD is now struggling to do the same.The chipsets from P35 forward take greater advantage of the current Intel system and of course the public is being fed the design slowly. The jump to DDR3 regardless of the terminology used or how accurate the term may be in a silly side-step discussion is required to increase the bandwidth and allow the next gen to function as designed. Class Dismissed