Interesting, yet wrong socket then? Or is it impractical to design two different chips with different L3 cache sizes for user vs. server markets? (I thought the Xeon chips were for servers.)Cheers,- jahman.

You don't generally need more pins to drive more cache, if that's what you're asking. Intel makes different sockets for the workstation/server markets compared to consumer products as another means of segmentation. IOW: they make more money this way

You don't generally need more pins to drive more cache, if that's what you're asking. Intel makes different sockets for the workstation/server markets compared to consumer products as another means of segmentation. IOW: they make more money this way

I agree (the "wrong socket" was me failing at being facetious.)What I meant was that it seem it's more practcical for Intel to segment the market via socket pin count than by adjusting L3 cache size (and gaining the benfit$ of reduced chipsize).Cheers,- jahman.

I agree (the "wrong socket" was me failing at being facetious.)What I meant was that it seem it's more practcical for Intel to segment the market via socket pin count than by adjusting L3 cache size (and gaining the benfit$ of reduced chipsize).Cheers,- jahman.

Ah, I see what you're saying. Yes, it is more effective for Intel to do things the way they do them. AMD had to take the same approach when they introduced the Opteron back in 2003. Cache size is one of the few differentiators between otherwise identical products on different sockets, though even that seems to be lessened much of late. More recently we have chips with greater core counts (Nehalem EX, Westermere EX) which also have correspondingly larger caches.